1. Field of the Invention
This invention relates to an improved process for forming MOS devices in a VLSI structure on a semiconductor wafer. More particularly, this invention relates to an improved process for producing optimized intrinsic, long channel, and short channel NMOS devices, as well as PMOS devices, in a VLSI structure on a semiconductor wafer without additional steps and masks.
2. Description of the Related Art
In the construction of MOS devices in VLSI structures, it is necessary to highly dope the channels of the short channel NMOS devices to prevent punchthrough due to the device scaling used in VLSI technology. At the same time, however, it is desirable to also form intrinsic NMOS devices with low threshold voltages in the VLSI structure for use, for example, as pass gates to minimize voltage drops. It is also desirable to form either intrinsic NMOS or long channel NMOS and PMOS devices with low body factor. Body factor is a term used to describe the characteristic of individual MOS devices in series with one another to exhibit a rise in individual threshold voltages. Low body factor results in lower individual threshold voltages exhibited by such devices in series resulting in optimum speed of the devices.
Since punchthrough has to be controlled for short channel devices, prior art processes used for the simultaneous construction of intrinsic, long channel, and short channel NMOS devices are conventionally optimized to provide highly doped short channel NMOS devices for punchthrough protection which results in compromising the long channel and intrinsic NMOS devices with respect to higher threshold voltage, and compromising the long channel NMOS devices with respect to higher body factor. The alternate prior art practice has been to introduce additional steps and masks into the process to protect those areas of the semiconductor wafer where intrinsic and long channel NMOS devices and PMOS devices will be constructed and optimized separately, during doping of the wafer to form the heavily doped short channel NMOS regions. This can increase the manufacturing costs.
It would, therefore, be highly desirable to have a process wherein punchthrough protection for short channel NMOS devices, low threshold voltage for intrinsic NMOS devices, and low body factor for long channel NMOS and PMOS devices could all be achieved without adding additional steps or masks to the process of forming such devices.